ASIC and System Key Laboratory Lecture 8
“Big Data” and Its Impact on Server and High Speed Link Design
Reporter: Xingchao (Chuck) Yuan
Time & Date：10:00 —11:00， Jun. 25, 2012
Place: Room 389, Microelectronics Building, Zhangjiang Campus, Fudan University
Abstract
According to a 2011 McKinsey’s research report, “big data” is the next frontier for innovation, competition, and productivity. Enormous amount of value could be captured: for example, $300B/year for US healthcare, $350B for Europe’s public sector administration, $600B/year consumer surplus, and finally ~2 million jobs created in US alone.
This presentation consists of two parts. In the first part, we will fly at “10,000” meters by answering the following questions:
What is the “big data”?
What kind of computing technologies and infrastructures does it require?
What type of challenges one needs to overcome?
What does it mean for designing servers and particularly high speed links?
After reviewing the modern internet architecture, we identify three major (hardware design) challenges that one must overcome in order to enable the “big data” applications:
Power “wall”:
100’s megawatts are consumed by a single datacenter
Interconnect “wall”
100’s thousands of servers need to be interconnected at high speed
Memory and storage “wall”
Virtualization and multicore demand more memory capacity and bandwidth
Memory (DRAM/Flash) density scaling is slowing and ending in a few years
By examining a few examples, we explore how various technology and techniques could be used to address these challenges. Specifically, we will review and compare several server architectures from Intel, IBM, and SeaMicro (AMD). We also show a few examples how 3D packaging, photonics, and new memory technology could be deployed to ease the scaling pain. Through these examples, the importance of interconnect is emphasized.
In the second part of the presentation, we come down to earth by describing how one could “scale” the interconnect wall. That is, we dive deeply into designing the high speed memory and chip to chip interconnects, or high speed links. In particular, we will present a high level design and modeling methodology for achieving aggressive design targets. The statistical link modeling methodology is presented. This is followed by presenting a methodology for modeling power supply noise induced jitter. We illustrate the effectiveness of the discussed methodologies by presenting two next generation memory system design examples:
Low power: 3.2Gbps mobile memory
High performance: 20Gbps graphics memory
We explain the special characteristics and requirements and describe the techniques to achieve the low power and high performance.
This presentation consists of two parts. In the first part, we will fly at “10,000” meters by answering the following questions:
What is the “big data”?
What kind of computing technologies and infrastructures does it require?
What type of challenges one needs to overcome?
What does it mean for designing servers and particularly high speed links?
After reviewing the modern internet architecture, we identify three major (hardware design) challenges that one must overcome in order to enable the “big data” applications:
Power “wall”:
100’s megawatts are consumed by a single datacenter
Interconnect “wall”
100’s thousands of servers need to be interconnected at high speed
Memory and storage “wall”
Virtualization and multicore demand more memory capacity and bandwidth
Memory (DRAM/Flash) density scaling is slowing and ending in a few years
By examining a few examples, we explore how various technology and techniques could be used to address these challenges. Specifically, we will review and compare several server architectures from Intel, IBM, and SeaMicro (AMD). We also show a few examples how 3D packaging, photonics, and new memory technology could be deployed to ease the scaling pain. Through these examples, the importance of interconnect is emphasized.
In the second part of the presentation, we come down to earth by describing how one could “scale” the interconnect wall. That is, we dive deeply into designing the high speed memory and chip to chip interconnects, or high speed links. In particular, we will present a high level design and modeling methodology for achieving aggressive design targets. The statistical link modeling methodology is presented. This is followed by presenting a methodology for modeling power supply noise induced jitter. We illustrate the effectiveness of the discussed methodologies by presenting two next generation memory system design examples:
Low power: 3.2Gbps mobile memory
High performance: 20Gbps graphics memory
We explain the special characteristics and requirements and describe the techniques to achieve the low power and high performance.
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Biography
Xingchao (Chuck) Yuan received his B.S. degree in Electronic Engineering from Nanjing Institute of Technology (now Southeast University), Nanjing, China, in 1982. He received both his M.S. and Ph.D. degrees in Electrical Engineering from Syracuse University, Syracuse, New York, in 1983 and 1987, respectively. After receiving his Ph.D., Dr. Yuan was at the Thayer School of Engineering at Dartmouth College; first as a Postdoctoral fellow, and later as a Research Assistant Professor from 1987 to 1990.
From 1990 to 1995, Dr. Yuan was employed by Ansoft Corp., where he led the development of Ansoft’s flagship product HFSSTM (High Frequency Structure Simulator). His work led to three different product releases, which included features such as modeling conductor and dielectric loss, radiation and periodic boundary conditions for modeling antennas, and electromagnetic scattering/interference problems. He pioneered a fast frequency sweep method that combined a finite element method and an asymptotic waveform evaluation method. This led to a dramatic speed improvement in the speed of 3D full-wave modeling. From 1995 to 1998, Dr. Yuan was with Cadence Corp. where he led the research and development of the signal integrity and EMI tools. His work focused on modeling SSO noise and induced electromagnetic interference, which led to some of the earliest research in power plane modeling.
Since 1998, Dr. Yuan has been with Rambus Inc, Sunnyvale, California, as a director of signal integrity engineering. Dr Yuan is responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies using conventional interconnect technologies. His technical and managerial leadership at Rambus has led to an industry-recognized signal and power integrity team of experts. Rambus’ SI/PI papers are closely followed by the rest of the industry, and represent the latest developments in high-performance signal and power integrity modeling and design. Dr. Yuan’s team was among the first to apply BER and statistical methodology to memory interface designs, and to explore the relationship between the supply noise spectrum and the jitter spectrum. His team’s work led to the successful development of Rambus’ XDR memory architecture, which was adopted by PlayStation 3, DLP projectors, and DTVs. Since 2009, Dr. Yuan has served as an engineering director in charge of a silicon team with dozens of engineers (in both the U.S. and India) who are responsible for designing next-generation Rambus graphics and main memory interfaces. In 2010, the team taped out a multi-modal PHY that explores the limits of single-ended signaling beyond 12.8Gbps, a power efficient differential interface at 20Gbps, and backward compatibility with existing memory interfaces (including GDDR5 and DDR3). Early in 2012, Dr. Yuan is promoted to Senior Director, Strategic Corporate Development, M&A.
Dr. Yuan has authored more than 130 papers in technical journals and conferences and holds 8 issued U.S. patents. He is a senior member of IEEE, and served on the technical program committee of IEEE EPEPS from 2008 to 2009.